1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to a method of fabricating an insulating film with different thicknesses for given transistor devices.
2. Description of the Related Art
In a conventional process flow for forming a typical field effect transistor, a gate oxide layer is grown on a lightly doped silicon substrate and a layer of polysilicon is deposited on the gate oxide layer. The polysilicon and the gate oxide are then anisotropically etched back to the upper surface of the substrate leaving a polysilicon gate electrode stacked on top of a gate oxide layer. Following formation of the polysilicon gate electrode, a source and a drain are formed by implanting a dopant species into the substrate. The gate electrode acts as a hard mask against the implant so that the source and drain are formed in the substrate self-aligned to the gate electrode. Many conventional semiconductor fabrication processes employ a double implant process to form the source and drain, one implant to establish lightly doped drain structures and the other to establish overlapping heavier doped regions. The substrate is then annealed to activate the dopant in the source and the drain. Salicidation steps frequently follow the formation of the source and drain.
The gate dielectric formation aspects of conventional transistor fabrication present certain disadvantages. Silicon dioxide gate oxide layers are made as thin as possible to maximize drive current and to control short channel effects. The requirement for very thin gate oxide layers has become particularly important in sub-micron processing where process scaling has dramatically increased the potential for short channel effects. However, the scaling of silicon dioxide gate dielectric layers has introduced another set of problems. As the thickness of silicon dioxide is scaled downward, the potential for reliability problems associated with dielectric breakdown and hot-carrier-injection degradation increases. Hot carrier degradation can significantly reduce device performance, while dielectric breakdown can lead to complete device failure. Gate current from drain to gate is another drawback. The phenomenon is particularly prevalent at the lower corners of a gate electrode where the electric field density is highest. This gate current can contribute to circuit static leakage current and result in excessive power and heat generation.
Increasing the amount of the insulating material or utilizing high-k dielectrics between the gate corners and source/drain regions can reduce leakage currents. However, such techniques can reduce the switching speed of the transistor or present process integration challenges.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
In accordance with one aspect of the present invention, a method of manufacturing is provided that includes forming first and second gate stacks on a substrate and forming an insulating layer on the substrate. The insulating layer has portions adjacent to the first gate stack and portions adjacent to the second gate stack. A first pair of insulating structures is formed adjacent to the first gate stack and a second pair of insulating structures is formed adjacent to the second gate stack. The first pair of insulating structures is removed. The portions of the insulating layer adjacent to the first gate stack are thickened while the second pair of insulating structures prevents thickening of the portions of the insulating layer adjacent to the second gate stack.
In accordance with another aspect of the present invention, a method of manufacturing is provided that includes forming a speed path critical gate stack and a non-speed path critical gate stack on a substrate. An insulating layer is formed on the substrate. The insulating layer has portions adjacent to the speed path critical gate stack and portions adjacent to the non-speed path critical gate stack. A first pair of insulating structures is formed adjacent to the speed path critical gate stack and a second pair of insulating structures is formed adjacent to the non-speed path critical gate stack. The second pair of insulating structures is removed. The portions of the insulating layer adjacent to the non-speed path critical gate stack are thickened while the second pair of insulating structures prevents thickening of the portions of the insulating layer adjacent to the speed path critical gate stack.
In accordance with another aspect of the present invention, a method of manufacturing is provided that includes forming a speed path critical gate stack and a non-speed path critical gate stack on a substrate. An oxide layer is formed on the substrate by oxidation. The oxide layer has portions adjacent to the speed path critical gate stack and portions adjacent to the non-speed path critical gate stack. A first pair of silicon nitride structures is formed adjacent to the speed path critical gate stack and a second pair of silicon nitride structures is formed adjacent to the non-speed path critical gate stack. The second pair of silicon nitride structures is removed. The portions of the oxide layer adjacent to the non-speed path critical gate stack are thickened while the second pair of silicon nitride structures prevents thickening of the portions of the oxide layer adjacent to the speed path critical gate stack.